Inverting Buck-Boost DCDC Converter Design Challenges

Inverting Buck-Boost DCDC Converter Design Challenges

Karim El khadiri and Hassan Qjidaa SidiMouhamed Ben Abdellah University, Morocco

ABSTRACT

This paper presents an inverting buck-boost DCDC converter design. A negative supply voltage is needed in a variety of applications, but only a few DCDC converters are available on the market. OLED, a new display type especially suited for small digital camera or mobile phone displays. Design challenges that came up when negative voltages have to be handled on chip will be discussed, such as continuous/discontinuous mode transition problems, negative voltage feedback and negative over-voltage protection. Both devices operate in a fixed frequency PWM mode or alternatively in PFM mode. The single inductor topology is called inverting buck-boost converter or simply inverter. The proposed converter has been implemented with a TSMC 0.13-um 2P4M CMOS process, and the chip area is 325 x 300 um2.

KEYWORDS Buck–boost converter ,DCM / CCM detection, Negative supply voltage. Original Source URL: http://airccse.org/journal/ijesa/papers/4114ijesa01.pdf http://airccse.org/journal/ijesa/current2014.html

Project-Based Microcontroller System Laboratory Using BK300 Development Board With PIC16F887 Chip

Project-Based Microcontroller System Laboratory Using BK300 Development Board With PIC16F887 Chip

Lukman A.Ajao1, Olayemi M.Olaniyi2, Jonathan G.Kolo2, Abdulazeez O.Ajao2 1Federal University of Technology, Nigeria 2Federal Polytechnic, Nigeria

ABSTRACT

Microcontroller system is one of the vital subjects offered by students during the sequence of study in universities and other colleges of science, engineering and technology in the world. In this paper, we solve the problem of student comprehension and skill development in embedded system design using microcontroller chip PIC16F887 by demonstration of hands-on laboratory experiments. Also, developments of software code, circuit diagram simulation were carried out. This is to help students connect their theoretical knowledge with the practical experience. Each of the experiments was carried out using BK300 development board, PICKit3 programmer, Proteus 8.0 software. Our years of experience in the teaching of microcontroller course and the active involvement of students as manifested in complete indepth hands-on laboratory projects on real life problem solving. Laboratory session with the development board and software demonstrated in this article is unambiguous. Future embedded system laboratory session could be designed around ATMel lines of Microcontrollers

KEYWORDS Microcontroller, Embedded system, Hands-on lab experiments, simulation, and PICKit3 programmer Original Source URL: http://airccse.org/journal/ijesa/papers/5315ijesa02.pdf http://airccse.org/journal/ijesa/current2015.html

Dynamic HW Priority Queue Based Schedulers for Embedded System

Dynamic HW Priority Queue Based Schedulers for Embedded System

Dinesh G Harkut and M.S. Ali Prof Ram Meghe College of Engineering & Management, India Professor, IIITM-K, Trivandrum, India

ABSTRACT

A real-time operating system (RTOs) is often used in embedded system, to structure the application code and to ensure that the deadlines are met by reacting on events by executing the functions within precise time. Most embedded systems are bound to real-time constraints with determinism and latency as a critical metrics. RTOs are generally implemented in software, increases computational overheads, jitter and memory footprint. Modern FPGA technology, enables the implementation of a full featured and flexible hardware based RTOs, which helps in reducing to greater extent these overheads even if not remove completely. Scheduling algorithms play an important role in the design of real-time systems. An Adaptive Fuzzy Inference System (FIS) based scheduler framework proposed in this article is based on the study and conclusion drawn from the research over the years in HW SW co-design domain. The proposed novel two phase FIS based adaptive hardware task scheduler minimizes the processor time for scheduling activity which uses fuzzy logic to model the uncertainty at first stage along with adaptive framework that uses feedback which allows processors share of task running on multiprocessor to be controlled dynamically at runtime. This Fuzzy logic based adaptive hardware scheduler breakthroughs the limit of the number of total task and thus improves efficiency of the entire real-time system. The increased computation overheads resulted from proposed two phase FIS scheduler can be compensated by utilising the basic characteristics of parallelism of the hardware as scheduler being migrated to FPGA. .

KEYWORDS Hardware scheduler, Job priority, Real-time operating system, Reconfigurable computing, Scheduling Algorithms, ANFIS, HW/SW co design. Original Source URL: http://aircconline.com/ijesa/V5N4/5415ijesa01.pdf http://airccse.org/journal/ijesa/current2015.html

Dynamut: A Mutation Testing Tool for Industry-Level Embedded System Applications

Dynamut: A Mutation Testing Tool for Industry-Level Embedded System Applications

Darin Weffenstette and Kristen R. Walcott University of Colorado, USA

ABSTRACT

Test suite evaluation is important when developing quality software. Mutation testing, in particular, can be helpful in determining the ability of a test suite to find defects in code. Because of challenges incurred developing on complex embedded systems, test suite evaluation on these systems is very difficult and costly. We developed and implemented a tool called DynaMut to insert conditional mutations into the software under test for embedded applications. We then demonstrate how the tool can be used to automate the collection of data using an existing proprietary embedded test suite in a runtime testing environment. Conditional mutation is used to reduce the time and effort needed to perform test quality evaluation in 48% to 67% less time than it would take to perform the testing with a more traditional mutate-compile-test methodology. We also analyze if testing time can be further reduced while maintaining quality by sampling the mutations tested.

KEYWORDS Test Development, Embedded Test Suites, Test Case Sampling, Mutation Testing Original Source URL: https://wireilla.com/ijesa/abstract/8318ijesa02.html https://wireilla.com/ijesa/current.html

Design of an Autonomous Smart Shower With Sensors and Actuators

Design of an Autonomous Smart Shower With Sensors and Actuators

Tareq Khan Eastern Michigan University, USA

ABSTRACT

At the beginning of taking a shower, the user needs to manually adjust a rotational handle or the ratio of cold and hot water to get the desired water temperature and the flow rate. In this paper, a temperature and flow rate sensor feedback smart shower is proposed which takes the target water temperature and flow rate from the user as input, and then automatically adjusts the ratio of the cold and the hot water during the shower to keep the temperature and flow rate fixed - even though there is fluctuation of supply water temperature and pressure. The proposed system contains distance sensor and automatically turns off the shower when the user is away for soaping or shampooing. The system generates a report on water usage and shower time – to promote awareness on saving water. An embedded system based prototype of the proposed shower has been developed and tested

KEYWORDS Ball valve, Embedded system, Finite State Machine, Sensor, Servo motor. Original Source URL: http://wireilla.com/papers/ijesa/8318ijesa01.pdf https://wireilla.com/ijesa/current.html

Development of Low Cost Private Office Access Control System (OACS)

Development of Low Cost Private Office Access Control System (OACS)

Sadeque Reza Khan Prime University, Bangladesh

ABSTRACT

Over the years, access control systems have become more and more sophisticated and several securitymeasures have been employed to combat the menace of insecurity of lives and property. This is done bypreventing unauthorized entrance into buildings through entrance doors using conventional and electroniclocks, discrete access code, and biometric methods such as the finger prints, thumb prints, the iris andfacial recognition. We have designed a flexible and low cost modular system based on integration ofkeypad, magnetic lock and a controller. PIC 16F876A which is an 8-bit Microcontroller, is used here as amain controller. An advanced simulation based compiler Flowcode V4 is used to develop the software part in this project.

KEYWORDS PIC; Keypad; Electromagnetic Lock; LCD; Flowcode Original Source URL: http://airccse.org/journal/ijesa/papers/2212ijesa01.pdf https://wireilla.com/ijesa/vol2.html

Real Time Monitoring and Control of Wireless Networks

Real Time Monitoring and Control of Wireless Networks

Girish Revadigar1 and Chitra Javali2 1Allgo Embedded Systems, India 2PES Institute of Technology, India

ABSTRACT

Adhoc sensor networks consists of dense wireless network having tiny, low-cost sensor nodes which collectthe environmental data and send it to the base station. Using such networks helps in monitoring andcontrol of physical environments remotely with ease and accuracy. Examples include military applications,and acquiring sensing information from inhospitable locations like thick forests, active volcano regions etc.Since the devices will be battery powered and are scattered in a complex network, It is very difficult to locate each node, know about its status and how the devices are connected in the wireless network.Because of their increased importance and applications, wireless networks are becoming part and parcelof our day to day life, and hence the need of developing a system to visualise , control and monitor suchnetworks arises. This paper presents implementation issues and author's contribution to design andimplement a generic framework of the 'Network Visualization tool' to monitor adhoc wireless networks.The paper also elaborates system architecture, hardware and software organizations, and integrationdetails of the proposed system with an exemplary wireless network based on standard IEEE 802.15.4 MACprotocol[1] to monitor temperature of different rooms in a house.

KEYWORDS Adhoc Wireless Networks, IEEE 802.15.4 MAC, Network Visualization . Original Source URL: http://airccse.org/journal/ijesa/papers/2112ijesa03.pdf https://wireilla.com/ijesa/vol2.html

Effect of Thread Level Parallelism on the Performance of Optimum Architecture for Embedded Applications

Effect of Thread Level Parallelism on the Performance of Optimum Architecture for Embedded Applications

Mehdi Alipour1 and Hojjat Taghdisi2 1Allameh Rafiei Highr Education Institute of Qazin, Iran 2Qazvin Islamic Azad University, Iran

ABSTRACT

According to the increasing complexity of network application and internet traffic, network processor as asubset of embedded processors have to process more computation intensive tasks. By scaling down thefeature size and emersion of chip multiprocessors (CMP) that are usually multi-thread processors, theperformance requirements are somehow guaranteed. As multithread processors are the heir of uni-threadprocessors and there isn’t any general design flow to design a multithread embedded processor, in thispaper we perform a comprehensive design space exploration for an optimum uni-thread embeddedprocessor based on the limited area and power budgets. Finally we run multiple threads on thisarchitecture to find out the maximum thread level parallelism (TLP) based on performance per power and area optimum uni-thread architecture.

KEYWORDS Embedded processor; cache; register file; multithread architecture; performance per power Original Source URL: http://airccse.org/journal/ijesa/papers/2112ijesa02.pdf https://wireilla.com/ijesa/vol2.html

FPGA Real Time Acceleration for Discrete Wavelet Transform of the 5/3 Filter for JPEG2000 Standard

FPGA Real Time Acceleration for Discrete Wavelet Transform of the 5/3 Filter for JPEG2000 Standard

Taoufik Saidani, Mohamed Atri, Yahia Said and Rached Tourki FSM University, Tunisia

ABSTRACT

In recent years video and image compression have became very required . The availability of powerful software design tools is a fundamental requirement to take advantage of the many advanced and specialized resources included in the latest devices. Video acceleration and processing technologies have become critical for the development of many consumer electronics products. In this paper, we investigate Real Time FPGA implementation of 2-D lifting-based Daubechies 5/3 transforms using a Matlab/Simulink/Xilinx System Generator tool that generates synthesizable VHSIC Hardware Description. This system offers significant advantages: portability, rapid time to market and real time, continuing parametric change in the DWT transform.The proposed model has been designed and simulated using Simulink and System Generator blocks, synthesized with Xilinx Synthesis tool (XST) and implemented on Spartan 3A DSP based XCSD 3400A-4fg476 target device.

KEYWORDS JPEG2000 ,wavelet , FPGA, Matlab Xilinx System generator, VHDL. Original Source URL: http://airccse.org/journal/ijesa/papers/2112ijesa01.pdf https://wireilla.com/ijesa/vol2.html

Socs Based Openrisc and Microblaze Soft Processors Comparison Study Cases: Audio Implementation and Network Implementation Based Socs

Socs Based Openrisc and Microblaze Soft Processors Comparison Study Cases: Audio Implementation and Network Implementation Based Socs

Faroudja Abid, Nouma Izeboudjen, Dalila Lazib, Mohamed Bakiri, Sabrina Titri and Fatiha Louiz Microelectronic and Nanotechnology Laboratory, Algeria

ABSTRACT

The IP reuse approach and FPGA-platform-based SoC (System on Chip) with an embedded soft processor is an alternative to design SoCs that allows fast creation and verification. In this paper we address a comparison study between two SoCs architectures based OpenRISC (OpenCores) and MicroBlaze (proprietary) soft processors. The comparison is done for two applications, namely the audio and network applications based SoCs. The SoCs have been prototyped using the Virtex5 XC5VLX50 FPGA. Regarding the SoCs for audio application, the results show that slices are more used in the Open RISC based SoC while BRAM memories are more used in the SoC based MicroBlaze. Concerning the SoCs for Network application used slices register are slightly different in the two SoCs, BRAM memories and slice LUTs are more used in the OpenRISC based SoC. We notice that power consumption is better for the SoCs based MicroBlaze for the both applications

KEYWORDS Audio, AC97 controller, Embedded system, FPGA, MicroBlaze, Power consumption, System on Chip (SoC), OpenCores, OpenRISC Original Source URL: http://airccse.org/journal/ijesa/papers/3413ijesa02.pdf https://wireilla.com/ijesa/vol3.html

Performing an Experimental Platform to Optimize Data Multiplexing

Performing an Experimental Platform to Optimize Data Multiplexing

Remy Astier, Thierry Capitaine, Jerome Dubois, Valery Bourny, Aurelien Lorthois and Jerome Fortin Laboratoire des Technologies Innovantes, France

ABSTRACT

This article is based on preliminary work on the OSI model management layers to optimized industrialwired data transfer on low data rate wireless technology. Our previous contribution deal with thedevelopment of a demonstrator providing CAN bus transfer frames (1Mbps) on a low rate wireless channelprovided by Zigbee technology. In order to be compatible with all the other industrial protocols, wedescribe in this paper our contribution to design an innovative Wireless Device (WD) and a software tool,which will aim to determine the best architecture (hardware/software) and wireless technology to be usedtaking in account of the wired protocol requirements. To validate the proper functioning of this WD, wewill develop an experimental platform to test different strategies provided by our software tool. We canconsequently prove which is the best configuration (hardware/software) compared to the others by theinclusion (inputs) of the required parameters of the wired protocol (load, binary rate, acknowledge timeout) and the analysis of the WD architecture characteristics proposed (outputs) as the delay introducedby system, buffer size needed, CPU speed, power consumption, meeting the input requirement. It will beimportant to know whether gain comes from a hardware strategy with hardware accelerator e.g or asoftware strategy with a more performing scheduler. At the end, our experimental platform will be a toolfor characterizing different WD

KEYWORDS Embedded system, Multiplexing, Decision Support Tool, Test bench, Networking management systems Original Source URL: http://airccse.org/journal/ijesa/papers/3413ijesa01.pdf https://wireilla.com/ijesa/vol3.html

Dominant Block Guided Optimal Cache Size Estimation to Maximize IPC of Embedded Software

Dominant Block Guided Optimal Cache Size Estimation to Maximize IPC of Embedded Software

Rajendra Patel and Arvind Rajawat Maulana Azad National Institute of Technology, India

ABSTRACT

Embedded system software is highly constrained from performance, memory footprint, energy consumptionand implementing cost view point. It is always desirable to obtain better Instructions per Cycle (IPC).Instruction cache has major contribution in improving IPC. Cache memories are realized on the same chipwhere the processor is running. This considerably increases the system cost as well. Hence, it is required tomaintain a trade-off between cache sizes and performance improvement offered. Determining the numberof cache lines and size of cache line are important parameters for cache designing. The design space forcache is quite large. It is time taking to execute the given application with different cache sizes on aninstruction set simulator (ISS) to figure out the optimal cache size. In this paper, a technique is proposed toidentify a number of cache lines and cache line size for the L1 instruction cache that will offer best ornearly best IPC. Cache size is derived, at a higher abstraction level, from basic block analysis in the LowLevel Virtual Machine (LLVM) environment. The cache size estimated from the LLVM environment is crossvalidated by simulating the set of benchmark applications with different cache sizes in SimpleScalar’s outof-ordersimulator. The proposed method seems to be superior in terms of estimation accuracy and/orestimation time as compared to the existing methods for estimation of optimal cache size parameters (cacheline size, number of cache lines).

KEYWORDS Optimal Cache Size, Embedded Software, Design Space Exploration, Performance Estimation, DominantBlock Original Source URL: http://airccse.org/journal/ijesa/papers/3313ijesa03.pdf https://wireilla.com/ijesa/vol3.html

Evaluating the Performance and Behaviour of RT-XEN

Evaluating the Performance and Behaviour of RT-XEN

Hasan Fayyad-Kazan1, Luc Perneel1 and Martin Timmerman1,2 1Vrije Universiteit Brussel, Belgium 2Dedicated-Systems Experts Diepenbeemd 5, Belgium

ABSTRACT

Virtualization, together with real-time support emerges to be used in an increasing amount of use cases, varying from embedded systems to enterprise computing. One of the most popular open-source virtualization software’s is Xen. Its current implementation does not qualify it to be a candidate for timecritical systems. Researchers and developers extended it and claim the efficient usage of their versions in such systems. RT-Xen is one of these versions. It is a virtualization platform based on Compositional Scheduling and uses a suite of fixed-priority schedulers. This paper evaluates the performance and scheduling behaviour of RT-Xen. The test results show that only two proposed schedulers are suitable to be used for soft real-time applications.

KEYWORDS Embedded systems Original Source URL: http://airccse.org/journal/ijesa/papers/3313ijesa02.pdf https://wireilla.com/ijesa/vol3.html

Temporal Workload Analysis and its Application to Power-Aware Scheduling

Temporal Workload Analysis and its Application to Power-Aware Scheduling

Ye-In Seol1, Jeong-Uk Kim1 and Young-Kuk Kim2, 1Sangmyung University, South Korea 2Chungnam National University, South Korea

ABSTRACT

Power-aware scheduling reduces CPU energy consumption in hard real-time systems through dynamic voltage scaling(DVS). The basic idea of power-aware scheduling is to find slacks available to tasks and reduce CPU‟s frequency or lower its voltage using the found slacks. In this paper, we introduce temporal workload of a system which specifies how much busy its CPU is to complete the tasks at current time. Analyzing temporal workload provides a sufficient condition of schedulability of preemptive early-deadline first scheduling and an effective method to identify and distribute slacks generated by early completed tasks. The simulation results show that proposed algorithm reduces the energy consumption by 10-70% over the existing algorithm and its algorithm complexity is O(n). So, practical on-line scheduler could be devised using the proposed algorithm

KEYWORDS Power-aware Scheduling, Real-time Scheduling, Embedded Systems Original Source URL: http://airccse.org/journal/ijesa/papers/3313ijesa01.pdf https://wireilla.com/ijesa/vol3.html

Practical Implementation: Phase Lock Loop and a Feedback Loop Based Full Colour Laser Tv

Practical Implementation: Phase Lock Loop and a Feedback Loop Based Full Colour Laser Tv

Oumair Naseer1, Atif Ali Khan1, Mian Naeem-ul-Haq2, Fawad Saleem2 and Ayesha Naseer3 1University of Warwick, UK 2FAST-nu, Pakistan 3NUST, Pakistan

ABSTRACT

In Multimedia society, the needs for large area display are increasing day by day. Many kinds of projection displays are now developed such as LCD, LCOS, DMD and Laser TV. Current Laser scanning projections methodologies is not efficient from cost, weight and power perspective. In this paper we have used low commercial microcontrollers with a scanning mirror (Progressive Scanning) technology. Three laser lights blue, green and red with wavelengths 457 nm, 532 nm and 648 nm are used. Power levels of lasers are adjusted for white color balance. Phase Lock Loop (PLL) with a feedback loop is used to synchronize horizontal (high speed brush-less DC motor) and vertical mirrors (stepper motor) pulses. The resulting Laser TV assembly is more efficient in terms of cost, power and weight

KEYWORDS Phase Lock Loop; Voltage Controlled Oscillation; Laser TV, Progressive Scanning. Original Source URL: http://airccse.org/journal/ijesa/papers/3213ijesa03.pdf https://wireilla.com/ijesa/vol3.html

A New N-Fold Flip-Flop with Output Enable

A New N-Fold Flip-Flop with Output Enable

Mounir Zid1, Carlo Pistritto2, Rached Tourki1 and Alberto Scandurra2 1University of Monastir, Tunisia 2On Chip Communication Systems, Italy

ABSTRACT

With the evolution of the semiconductor industry and the continuous growing demands for high performance VLSI circuit, the aggressive scaling in feature size and high integration density along with the high operating frequencies make power consumption and digital noise in modern analog and digital devices one of the top concerns of Very Large Scale Integration (VLSI) circuit design. In this paper we delve into the design of n-fold flip-flops with output enable. A new n-fold flip-flop exploiting the clock gating technique for both outputs enabling and power saving is presented. To evaluate its performance, an octal flip-flop was built according to the new proposed structure and compared to the main octal flip-flops used today. The different flip-flops were implemented in STMicroelectronics 65 nm process technology and simulated for the worst case condition where the switching activity is maximal. Post layout simulation showed that the new circuit provides the same functional performances as conventional solutions with significantly less power consumption, area and digital noise

KEYWORDS Flip-flops; Output enabling; Low power design; Clock gating Original Source URL: http://airccse.org/journal/ijesa/papers/3213ijesa02.pdf https://wireilla.com/ijesa/vol3.html

Design of a Battery Charger Interface Precharge for Mobile Phone

Design of a Battery Charger Interface Precharge for Mobile Phone

Karim El khadiri and Hassan Qjidaa Sidi Mouhamed Ben Abdellah University, Morocco

ABSTRACT

This paper describes the analysis and design of a Battery Charger Interface Pre-charge (BCIP) for mobile phone. Battery charger interface pre-charge is very important function in the battery management integrated circuit, which allows the control of the charge of the battery with the maximum battery autonomy without reducing its life. The Battery Charger Interface Pre-charge has been designed and implemented in a 0.35µm CMOS technology and the active area of this circuit is about 1.54mm2

KEYWORDS Battery charger interface, Pre-charge, Band-gap, Comparator, Shunt-regulator Original Source URL: http://airccse.org/journal/ijesa/papers/3213ijesa01.pdf https://wireilla.com/ijesa/vol3.html

Experimental Implementation of Embarrasingly Parallel Process in Analysis of Blood Glucose Concentration Using Atmega32 Microcontrollers

Experimental Implementation of Embarrasingly Parallel Process in Analysis of Blood Glucose Concentration Using Atmega32 Microcontrollers

S. Kumaravel1 and P. Neelamegam2 1AVVM Sri Pushpam College (Autonomous), India 2Technology and Research Academy (SASTRA) Deemed University, India

ABSTRACT

This paper explains the development of a embedded based parallel system to measure glucose concentration of the blood samples. The developed instrument works on the principle of absorbance transmittance photometry using ATmega32 microcontrollers. In order to handle more blood samples and reduce the response time of glucose analyzing process in large number of blood samples, the embarrassing parallel measurement operation is implemented. The proposed system architecture and the co-design of hardware and software are discussed in detail. The system is evaluated using the parameters of Speedup Factor, Efficiency and Throughput are studied. The result shows that system attained the linear speedup in measurement of blood samples.

KEYWORDS Parallel Process, Embedded System, Glucose Concentration, Microcontroller, Clinical Blood Analyzer. Original Source URL: http://airccse.org/journal/ijesa/papers/3113ijesa04.pdf https://wireilla.com/ijesa/vol3.html

Hardware Acceleration of the Gipps Model for Real-Time Traffic Simulation

Hardware Acceleration of the Gipps Model for Real-Time Traffic Simulation

Salim Farah and Magdy Bayoumi, University of Louisiana at Lafayette, USA

ABSTRACT

Traffic simulation software is becoming increasingly popular as more cities worldwide use it to better manage their crowded traffic networks. An important requirement for such software is the ability to produce accurate results in real time, requiring great computation resources. This work proposes an ASICbased hardware accelerated approach for the AIMSUN traffic simulator, taking advantage of repetitive tasks in the algorithm. Different system configurations using this accelerator are also discussed. Compared with the traditional software simulator, it has been found to improve the performance by as much as 9x when using a single processing element approach, or more depending on the chosen hardware configuration.

KEYWORDS Traffic Simulation, Gipps Model, AIMSUN, ASIC Original Source URL: http://airccse.org/journal/ijesa/papers/3113ijesa03.pdf https://wireilla.com/ijesa/vol3.html

Hardware/Software Co-Design of a 2d Graphics System on FPGA

Hardware/Software Co-Design of a 2d Graphics System on FPGA

Kahraman Serdar Ay1 and Atakan Dodan2 1Tubitak Bilgem, Kocaeli, Turkey 2Anadolu University, Turkey

ABSTRACT

Embedded systems in several applications require a graphics system to display some application-specific information. Yet, commercial graphic cards for the embedded systems either incur high costs, or they are inconvenient to use. Furthermore, they tend to quickly become obsolete due to the advances in display technology. On the other hand, FPGAs provide reconfigurable hardware resources that can be used to implement graphics system in which they can be reconfigured to meet the ever-evolving requirements of graphics systems. Motivated from this fact, this study considers the design and implementation of a 2D graphics system on FPGA. The graphics system proposed is composed of a CPU IP core, peripheral IP cores (Bresenham, BitBLT, DDR Memory Controller, and VGA) and PLB bus to which CPU and all peripheral IP cores are attached. Furthermore, some graphics drivers and APIs are developed to complete the whole graphics creation process.

KEYWORDS Accelerator architectures, computer graphics, digital circuits, embedded software Original Source URL: http://airccse.org/journal/ijesa/papers/3113ijesa02.pdf https://wireilla.com/ijesa/vol3.html

Design and Implementation of a Wireless Sensor and Actuator Network for Energy Measurement and Control at Home

Design and Implementation of a Wireless Sensor and Actuator Network for Energy Measurement and Control at Home

Edwin Chobot, Daniel Newby, Renee Chandler, Nusaybah Abu-Mulaweh, Chao Chen and Carlos Pomalaza-Raez Indiana University - Purdue University Fort Wayne, USA

ABSTRACT

This paper describes the design, implementation, and testing of a wireless sensor and actuator network for monitoring the energy use of electric appliances in a home environment. The network includes energy measurement nodes and a central server, where the nodes read the energy use of connected appliance, and wirelessly report their readings to the central server for processing. The server displays the readings from these nodes via a user visual interface in real time. Through this system, users can easily understand their electricity usage patterns and adapt their behaviour to reduce their energy consumption and costs. Moreover, users are able to remotely power on/off individual devices to actively control the power use of certain appliances. The system allows for inexpensive monitoring of home energy use and illustrates a practical way to control the energy consumption through user interaction.

KEYWORDS Wireless sensor and actuator network, energy measurement, remote control, IEEE 802.15.4 Original Source URL: http://airccse.org/journal/ijesa/papers/3113ijesa01.pdf https://wireilla.com/ijesa/vol3.html

Automatic Analysis of Smoothing Techniques by Simulation Model Based Real-Time System for Processing 3D Human Faces

Automatic Analysis of Smoothing Techniques by Simulation Model Based Real-Time System for Processing 3D Human Faces

Suranjan Ganguly, Debotosh Bhattacharjee and Mita Nasipuri Jadavpur University, India

ABSTRACT

The pivotal research work that has been carried out and described in this literature acknowledges the importance of various smoothing techniques for processing 3D human faces from 2.5D range face images. The smoothing techniques have been developed and implemented using MATLAB-Simulink for real time processing in embedded system. In addition, the significance of smoothed 2.5D range image over original face range image has been discovered as well as its time complexity has also been reported with array of experiments. The variations in time complexities are also accomplished using different optimization levels and execution modes. A set of filtering techniques such as, Max filter, Min filter, Median filter, Mean filter, Mid-point filter and Gaussian filter, have been designed and illustrated using Simulink model. The model takes depth face image (i.e. the range face image) as input in real time and presents the improvement over original face images. In the design flow, the performance of every block has also been characterized by range face images from Frav3D, GavabDB, and Bosphorus databases. In the experimental section of this research article, an array of performance analysis for these smoothing techniques with variation of frameworks is explained.

KEYWORDS 3D face image, 2.5D face image, MATLAB-Simulink, Smoothing techniques, Range face image Original Source URL: http://airccse.org/journal/ijesa/papers/4414ijesa02.pdf http://airccse.org/journal/ijesa/current2014.html

A Case Study: Task Scheduling Methodologies for High Speed Computing Systems

A Case Study: Task Scheduling Methodologies for High Speed Computing Systems

Mahendra Vucha and Arvind Rajawat Maulana Azad National Institute of Technology, India

ABSTRACT

High Speed computing meets ever increasing real-time computational demands through the leveraging of flexibility and parallelism. The flexibility is achieved when computing platform designed with heterogeneous resources to support multifarious tasks of an application where as task scheduling brings parallel processing. The efficient task scheduling is critical to obtain optimized performance in heterogeneous computing Systems (HCS). In this paper, we brought a review of various application scheduling models which provide parallelism for homogeneous and heterogeneous computing systems. In this paper, we made a review of various scheduling methodologies targeted to high speed computing systems and also prepared summary chart. The comparative study of scheduling methodologies for high speed computing systems has been carried out based on the attributes of platform & application as well. The attributes are execution time, nature of task, task handling capability, type of host & computing platform. Finally a summary chart has been prepared and it demonstrates that the need of developing scheduling methodologies for Heterogeneous Reconfigurable Computing Systems (HRCS) which is an emerging high speed computing platform for real time applications

KEYWORDS High Speed Computing Systems, Heterogeneous Computing System, homogeneous Computing System, Reconfigurable Hardware, Scheduling, soft core processor, hard core processor Original Source URL: http://airccse.org/journal/ijesa/papers/4414ijesa01.pdf http://airccse.org/journal/ijesa/current2014.html

Fast Transient Response Low Drop-Out Voltage Regulator

Fast Transient Response Low Drop-Out Voltage Regulator

Hicham Akhamal, Mostafa Chakir, Hassan Qjidaa Sidi Mohamed Ben Abdellah University, Morocco

ABSTRACT

This paper presents the design of Low Drop-Out (LDO) voltage regulator has fast transient response and which exploits a few current else low quiescent current in the operational amplifier PMOS type. We use band-gap reference for eliminate the temperature dependence. The proposed LDO voltage regulator implemented in 0.18-µm CMOS technology, we use Folded cascode CMOS amplifiers high performance in the stability , provide fast transient response which explains a fast settling, the LDO itself should provide in the output regulator voltages at ∆t equal 2ps with transient variation of the voltage less than 170mV. High accuracy in the DC response terms, the simulation results show that the accuracy of the output regulator voltages is 1.54±0.009V, and power consumption of 1.51 mW

KEYWORDS Low-dropout (LDO ) voltage regulator, Band-gap reference, Fast transient response, Current efficiency, Figure of merit & Layout. Original Source URL: http://airccse.org/journal/ijesa/papers/4314ijesa01.pdf http://airccse.org/journal/ijesa/current2014.html

Generic SOPC Platform for Video Interactive System with Mpmc Controller

Generic SOPC Platform for Video Interactive System with Mpmc Controller

Lamjed Touil1,2, Lilia Kechiche1,2 and Bouraoui Ouni1,3 1University of Monastir, Tunisia 2National Engineering School of Monastir (ENIM), Tunisia3National Engineering School of Sousse (ENISo), Tunisia

ABSTRACT

Today, a significant number of embedded systems focus on multimedia applications with almost insatiable demand for low-cost, high performance, and low power hardware cosumption. In this paper, we present a re-configurable and generic hardware platform for image and video processing. The proposed platform uses the benefits offered by the Field Programmable Gate Array (FPGA) to attain this goal. In this context, a prototype system is developed based on the Xilinx Virtex-5 FPGA with the integration of embedded processors, embedded memory, DDR, interface technologies, Digital Clock Managers (DCM) and MPMC. The MPMC is an essential component for design performance tuning and real time video processing. We demonstrate the importance role of this interface in multi video applications. In fact, to successful the deployment of DRAM it is mandatory to use a flexible and scalable interface. Our system introduces diverse modules, such as cut video detection, video zoom-in and out. This provides the utility of using this architecture as a universal video processing platform according to different application requirements. This platform facilitates the development of video and image processing applications.

KEYWORDS MPMC, DDR, Cut Detection, Zoom-in, Zoom-out RGB, Image Processing Original Source URL: http://airccse.org/journal/ijesa/papers/4114ijesa02.pdf http://airccse.org/journal/ijesa/current2014.html

Simple Hand-Held Calculating Unit to Aid the Visually Impaired with Voice Output

Simple Hand-Held Calculating Unit to Aid the Visually Impaired with Voice Output

Shreedeep Gangopadhyay, Molay Kumar Mondal and Arpita Pramanick Techno India, Salt Lake, India Professor, IIITM-K, Trivandrum, India

ABSTRACT

A thorough understanding in mathematics enhances educational and occupational opportunities for all,whether sighted or visually impaired.. However, solving complicated mathematical problems is difficult forvisually challenged students in schools and universities as the calculators available in the markets with smooth input keys and LCD outputs are useless for them. Using the assistive technology which is basicallya service or product to help people with disabilities function more independently has removed barriers toeducate and employ people. An optimal solution for them is Braille calculator with audio output. In thispaper, we have proposed a cost effective, hand-held, battery-driven, low power assistive device aiming thevisually impaired people from low income settings. The input is given through a 4 by 4 Membrane keypadwhich has been Braille-embossed using indigenous methods. The output is announced in natural English bythe audio unit via speakers and/or headphones up to two places of decimal point. The system is implemented on custom made open source Arduino platform, making it efficient and cost-effective.

KEYWORDS Braille Keypad, calculator, Arduino, assistive technology, visually challenged. Original Source URL: http://airccse.org/journal/ijesa/papers/5315ijesa01.pdf http://airccse.org/journal/ijesa/current2015.html

Design Challenges in Wireless Fire Security Sensor Nodes

Design Challenges in Wireless Fire Security Sensor Nodes

S.R.Vijayalakshmi and S.Muruganand Bharathiar University, India

ABSTRACT

A design of simple hardware circuit with differentkind of fire sensors enables every user to use thiswireless fire security system. The challenges in designing the nodes with various types of fire sensors arediscussed and the methods to overcome design proble ms are also analyzed. The circuit is interfaced withthe different types of sensor to sense different fire sources such as gas leakage, smoke, and heat. The cost,circuit components, design requirements, power requirements of sensor node are minimized. The methods to improve the quality of system to detect fire areanalyzed. The system is fully controlled by the PICmicrocontroller. All the sensors and detectors areinterconnected to PIC microcontroller by using varioustypes of interface circuits. The PIC microcontroller will continuously monitor all the sensors and ifit sensesany security problem then the microcontroller willsend the information to the PC central monitoringstation wirelessly for a short distance of 300m indoor/1500m outdoor using zigbee technology. The gassensor, light sensor, smoke detector sensor, IR sensor, temperature & humidity sensor, fire sensor areinterfaced with microcontroller to detect abnormalfire conditions in the environment in all possibleways

KEYWORDS Security Systems - Smoke Sensor – wireless sensor nodes – wireless fire security sensor nodes Original Source URL: http://airccse.org/journal/ijesa/papers/5215ijesa03.pdf http://airccse.org/journal/ijesa/current2015.html

Comparison and Evaluation of Digital Signature Schemes Employed in NDN Network

Comparison and Evaluation of Digital Signature Schemes Employed in NDN Network

Al Imem Ali H. Sousse University of Sousse, Tunisia

ABSTRACT

It is well known that Named Data networking ensure data integrity so that every important data has to besigned by its owner in order to send it safely inside the network. Similarly, in NDN we have to assure thatnone could open the data except authorized users. Since only the endpoints have the right to sign the data or check its validity during the verification process , we have considered that the data could be requested from various types of devices used by different people, these devices could be anything like a smartphone, PC, sensor node etc.b, with a different CPU descriptions, parameters, and memory sizes, however their ability to check the high traffic of a data during the key generation and/or verification period is definitely a hard task and it could exhaust the systems with low computational resources. RSA and ECDSA as digital signature algorithms have proven their efficiency against cyber-attacks, they are characterized by their speed to encrypt and decrypt data, in addition to their competence at checking the data integrity. The main purpose of our research was to find the optimal algorithm that avoids the system’s overhead and offers the best time during the signature scheme

KEYWORDS RSA, ECDSA, NDN, MSS, Digital signature algorithms, Security,Encryption, Decryption, Merkle scheme, Eliptic Curve Original Source URL: http://airccse.org/journal/ijesa/papers/5215ijesa02.pdf http://airccse.org/journal/ijesa/current2015.html

An Efficient Hybrid Scheduler Using Dynamic Slack for Real-Time Critical Task Scheduling in Multicore Automotive ECUs

An Efficient Hybrid Scheduler Using Dynamic Slack for Real-Time Critical Task Scheduling in Multicore Automotive ECUs

Geetishree Mishra1, Manasa RamPrasad2, Ashwin Itagi3 and K S Gurumurthy4, 1BMS College of Engineering, India, 2ABB India Limited, India3CISCO Systems, India 4Reva Intitute of Technology, India

ABSTRACT

Task intensive electronic control units (ECUs) in automotive domain, equipped with multicore processors ,real time operating systems (RTOSs) and various application software, should perform efficiently and time deterministically. The parallel computational capability offered by this multicore hardware can only be exploited and utilized if the ECU application software is parallelized. Having provided with such parallelized software, the real time operating system scheduler component should schedule the time critical tasks so that, all the computational cores are utilized to a greater extent and the safety critical deadlinesare met. As original equipment manufacturers (OEMs) are always motivated towards adding moresophisticated features to the existing ECUs, a large number of task sets can be effectively scheduled for execution within the bounded time limits. In this paper, a hybrid scheduling algorithm has been proposed,that meticulously calculates the running slack of every task and estimates the probability of meeting deadline either being in the same partitioned queue or by migrating to another. This algorithm was run and tested using a scheduling simulator with different real time task models of periodic tasks . This algorithmwas also compared with the existing static priority scheduler, which is suggested by Automotive OpenSystems Architecture (AUTOSAR). The performance parameters considered here are, the % of coreutilization, average response time and task deadline missing rate. It has been verified that, this proposedalgorithm has considerable improvements over the existing partitioned static priority scheduler based on each performance parameter mentioned above.

KEYWORDS ECU, Multicore, RTOS, Scheduling, OEM, AUTOSAR. Original Source URL: http://airccse.org/journal/ijesa/papers/5215ijesa01.pdf http://airccse.org/journal/ijesa/current2015.html

A Novel Methodology for Task Distribution in Heterogeneous Reconfigurable Computing System

A Novel Methodology for Task Distribution in Heterogeneous Reconfigurable Computing System

Mahendra Vucha1 and Arvind Rajawat2 1MANIT University India 2Christ University, India

ABSTRACT

Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems(HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core processors acts as computing elements. So, an efficient task distribution methodology is essential forobtaining high performance in modern embedded systems. In this paper, we present a novel methodologyfor task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a listbased dynamic scheduling algorithm that uses attributes of tasks as well computing resources as costfunction to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDMtransmitters are represented as task graph and then the task are distributed, statically as well dynamically,to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparisonshows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and alsospeedup an application execution

KEYWORDS Heterogeneous Reconfigurable Computing Systems, FPGA, parallel processing, concurrency, Directed Acyclic Graph. Original Source URL: http://airccse.org/journal/ijesa/papers/5115ijesa02.pdf http://airccse.org/journal/ijesa/current2015.html

Time Critical Multitasking For Multicore Microcontroller Using Xmos® Kit

Time Critical Multitasking For Multicore Microcontroller Using Xmos® Kit

Prerna Saini1, Ankit Bansal2 and Abhishek Sharma1, 1LNM Institute of Information Technology,India 2GLA University, India

ABSTRACT

This paper presents the research work on multicore microcontrollers using parallel, and time critical programming for the embedded systems. Due to the high complexity and limitations, it is very hard to work on the application development phase on such architectures. The experimental results mentioned in the paper are based on xCORE multicore microcontroller form XMOS®. The paper also imitates multi-tasking and parallel programming for the same platform. The tasks assigned to multiple cores are executed simultaneously, which saves the time and energy. The relative study for multicore processor and multicore controller concludes that micro architecture based controller having multiple cores illustrates better performance in time critical multi-tasking environment. The research work mentioned here not only illustrates the functionality of multicore microcontroller, but also express the novel technique of programming, profiling and optimization on such platforms in real time environments .

KEYWORDS Multicore microcontroller, xCORE, xTIMEcomposer, Multitasking, Parallel programming, Time slicing, Embedded System, Time critical programming. Original Source URL: http://airccse.org/journal/ijesa/papers/5115ijesa01.pdf http://airccse.org/journal/ijesa/current2015.html

DESIGN AND PROTOTYPE OF A WIRELESS TAILGATE DETECTION SYSTEM USING SUN SPOT PLATFORM

DESIGN AND PROTOTYPE OF A WIRELESS TAILGATE DETECTION SYSTEM USING SUN SPOT PLATFORM Andres Alarcon-Ramirez, Madeline Martinez-Pabón and Charles Kim Department of Electrical Engineering, Howard University, Washington DC ABSTRACT

In this paper, we present the design and implementation of a wireless sensor based piggybacking and tailgating detection system to detect unauthorized attempt to gain access to a secured area. A set of Sun SPOT wireless sensor platform is adopted for acceleration sensor, transmitter, and receiver units for the system. A wireless sensor embedded in a security door collects the signal of door movement constantly and transmits the signal wirelessly to another wireless sensor (base unit), which collects the transmitted signals and stores them in the memory of the computer system for analysis. The acceleration signal is analyzed in both time and frequency domain to detect and classify single and tailgate entries. The paper focuses on the description of the wireless sensor network and the sensor-based tailgate detection algorithm.

KEYWORDS Tailgate, piggybacking, embedded system, wireless sensor network, acceleration sensor. Original Source Link: http://airccse.org/journal/ijesa/papers/0811ijesa01.pdf http://wireilla.com/ijesa/vol1.html

A REVIEW ON ZIGBEE, GSM AND WSN BASED HOME SECURITY BY USING EMBEDDED CONTROLLED SENSOR NETWORK

A REVIEW ON ZIGBEE, GSM AND WSN BASED HOME SECURITY BY USING EMBEDDED CONTROLLED SENSOR NETWORK Anjali Kulkarni and Amol Patange Department of Electronics and Telecommunication Engineering, S.R.T.M University, India ABSTRACT

Embedded controlled detector network is that the technology needs to implement environmental solutions effectively. The wireless sensor network is used to control respective devices and monitor environmental parameters effectively. Wireless sensor network technology is used to monitor environmental parameters such temperature sound pressure in many applications. Many researchers are developed the wireless sensor network to implement real time surveillance for many applications. The existing wired systems are bulky, very high cost and difficult to maintain. The proposed system is user friendly, low cost and controlled by embedded controlled sensor network. In the proposed system ARM based microcontroller is used for monitoring and wireless sensors are used to control the various devices.

KEYWORDS

Zigbee, GSM, WSN, and Embedded controlled sensor network.

Original Source URL http://aircconline.com/ijesa/V6N4/6416ijesa01.pdf http://wireilla.com/ijesa/vol6.html

Developing Scheduler Test Cases To Verify Scheduler Implementations In Time-triggered Embedded Systems

Developing Scheduler Test Cases To Verify Scheduler Implementations In Time-triggered Embedded Systems

Mouaaz Nahas¹ and Ricardo Bautista-Quintero²

¹College of Engineering and Islamic Architecture, KSA, ²Department of Mechanical Engineering, InstitutoTecnólogico De Culiacán, Sinaloa

Abstract

Despite that there is a “one-to-many” mapping between scheduling algorithms and scheduler implementations, only a few studies have discussed the challenges and consequences of translating between these two system models. There has been an argument that a wide gap exists between scheduling theory and scheduling implementation in practical systems, where such a gap must be bridged to obtain an effective validation of embedded systems. In this paper, we introduce a technique called “Scheduler Test Case” (STC) aimed at bridging the gap between scheduling algorithms and scheduler implementations in single processor embedded systems implemented using Time-Triggered Co-operative (TTC) architectures. We will demonstrate how the STC technique can provide a simple and systematic way for documenting, verifying (testing) and comparing various TTC scheduler implementations on particular hardware. However, STC is a generic technique that provides a black-box tool for assessing and predicting the behavior of representative implementation sets of any real-time scheduling algorithm.

Keywords

Scheduler algorithm, scheduler implementation, cyclic executive, time-triggered co-operative scheduler, resource-constrained embedded system, scheduler test cases, predictability, jitter, task overrun.

Original Source URL: http://aircconline.com/ijesa/V6N1/6116ijesa01.pdf http://wireilla.com/ijesa/vol6.html

A Level Training Set with both a Computer-Based Control and a Compact Controller

A Level Training Set with both a Computer-Based Control and a Compact Controller

Hayati Mamur¹, Ismail Atacak², Fatih Korkmaz³ and M. R. Amin Bhuiyan¹

¹Manisa Celal Bayar University, Turkey, ²Gazi University, Turkey and ³Cankiri Karatekin University, Turkey

Abstract

In engineering education, the combination with theoretical education and practical education is an essential problem. The taught knowledge can be quickly forgotten without an experimental application. In addition, the theoretical knowledge’s cannot be easily associated applications by students when they start working in industry. To eliminate these problems, a number of education tools have been developed in engineering education. This article presents a modeling, simulation and practice study of a newly designed liquid level training set developed for the control engineering students to simulate, examine and analyze theoretically and experimentally the controllers widely used in the control of many industrial processes.The newly designed training set combines two control structures, which are a computer-based control and a digital signal processing-based control. The set displays the results related to experiments in real time as well as. These features have made it a suitable laboratory component on which the students can both simulate and test the performance of liquid level control systems by using theoretical different control structures.

Keywords

Computer-aided engineering, Computer-based control, DSP-based control, Engineering education, Process control

Original Source URL: http://aircconline.com/ijesa/V7N1/7117ijesa01.pdf http://wireilla.com/ijesa/current.html

Home

International Journal of Embedded Systems and Applications (IJESA)

ISSN : 1839 – 5171

http://wireilla.com/ijesa/index.html  

Scope & Topics

International Journal of Embedded Systems and Applications (IJESA) is a quarterly open access peer-reviewed journal that publishes articles which contribute new results in all areas of the Embedded Systems and applications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on understanding Embedded Systems and establishing new collaborations in these areas.

Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of Embedded Systems & applications.

Topics of interest include but are not limited to, the following

• Application-specific processors and devices
• Business Applications
• Component and binding models
• Embedded computing education
• Embedded hardware support
• Embedded software
• Embedded system architecture
• Hardware and software co-design
• Industrial practices and benchmark suites
• Integration with business logic
• Integration with SOA
• Middleware
• Networked Embedded Systems
• Policy-based management
• Programming abstractions
• Real-time systems
• Recent Trends
• Service-Oriented Architectures
• Testing techniques

Paper Submission

Authors are invited to submit papers for this journal through the Submission system. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates

• Submission Deadline    :  May 12, 2018
• Notification                  :  June 12, 2018
• Final Manuscript Due   : June 20, 2018
• Publication Date           : Determined by the Editor-in-Chief