Rajendra Patel and Arvind Rajawat Maulana Azad National Institute of Technology, India
ABSTRACT
Embedded system software is highly constrained from performance, memory footprint, energy consumptionand implementing cost view point. It is always desirable to obtain better Instructions per Cycle (IPC).Instruction cache has major contribution in improving IPC. Cache memories are realized on the same chipwhere the processor is running. This considerably increases the system cost as well. Hence, it is required tomaintain a trade-off between cache sizes and performance improvement offered. Determining the numberof cache lines and size of cache line are important parameters for cache designing. The design space forcache is quite large. It is time taking to execute the given application with different cache sizes on aninstruction set simulator (ISS) to figure out the optimal cache size. In this paper, a technique is proposed toidentify a number of cache lines and cache line size for the L1 instruction cache that will offer best ornearly best IPC. Cache size is derived, at a higher abstraction level, from basic block analysis in the LowLevel Virtual Machine (LLVM) environment. The cache size estimated from the LLVM environment is crossvalidated by simulating the set of benchmark applications with different cache sizes in SimpleScalar’s outof-ordersimulator. The proposed method seems to be superior in terms of estimation accuracy and/orestimation time as compared to the existing methods for estimation of optimal cache size parameters (cacheline size, number of cache lines).
KEYWORDS Optimal Cache Size, Embedded Software, Design Space Exploration, Performance Estimation, DominantBlock Original Source URL: http://airccse.org/journal/ijesa/papers/3313ijesa03.pdf https://wireilla.com/ijesa/vol3.html
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