Developing Scheduler Test Cases To Verify Scheduler Implementations In Time-triggered Embedded Systems

Developing Scheduler Test Cases To Verify Scheduler Implementations In Time-triggered Embedded Systems

Mouaaz Nahas¹ and Ricardo Bautista-Quintero²

¹College of Engineering and Islamic Architecture, KSA, ²Department of Mechanical Engineering, InstitutoTecnólogico De Culiacán, Sinaloa

Abstract

Despite that there is a “one-to-many” mapping between scheduling algorithms and scheduler implementations, only a few studies have discussed the challenges and consequences of translating between these two system models. There has been an argument that a wide gap exists between scheduling theory and scheduling implementation in practical systems, where such a gap must be bridged to obtain an effective validation of embedded systems. In this paper, we introduce a technique called “Scheduler Test Case” (STC) aimed at bridging the gap between scheduling algorithms and scheduler implementations in single processor embedded systems implemented using Time-Triggered Co-operative (TTC) architectures. We will demonstrate how the STC technique can provide a simple and systematic way for documenting, verifying (testing) and comparing various TTC scheduler implementations on particular hardware. However, STC is a generic technique that provides a black-box tool for assessing and predicting the behavior of representative implementation sets of any real-time scheduling algorithm.

Keywords

Scheduler algorithm, scheduler implementation, cyclic executive, time-triggered co-operative scheduler, resource-constrained embedded system, scheduler test cases, predictability, jitter, task overrun.

Original Source URL: http://aircconline.com/ijesa/V6N1/6116ijesa01.pdf http://wireilla.com/ijesa/vol6.html