Tuesday, 30 December 2025

9th International Conference on Electrical and Electronics Engineering (ICEEE 2026)

 #ElectronicsEngineering #ECE #Electronics #ElectricalEngineering #CircuitDesign #ElectronicCircuits #AnalogElectronics #DigitalElectronics #EmbeddedSystems #VLSI #Microelectronics #PowerElectronics #EmbeddedDesign #Microcontrollers #SmartDevices #ElectronicsInnovation

 

Submit your Research Articles!!!

 

Welcome To ICEEE

 

9th International Conference on Electrical and Electronics Engineering (ICEEE 2026)
March 30 ~ 31, 2026, Virtual Conference
https://iceee2026.org/

 

Submission Deadline: January 03, 2026

 

Contact us:
Here's where you can reach us : iceee@iceee2026.org or iceeeconf29@gmail.com

 

Submission URL: https://iceee2026.org/submission/index.php


7th International Conference on Signal Processing, VLSI Design & Communication Systems (SVC 2026)

 Submit Your Research Articles !!! 

7th International Conference on Signal Processing, VLSI Design & Communication Systems (SVC 2026) 
February 27 ~ 28, 2026, Vancouver, Canada
https://acsty2026.org/svc/index

 

Submission Deadline : January 03,2026
Paper Submission url : https://acsty2026.org/submission/index.php  

Allconf pro url: https://allconferencecfpalerts.com/cfp/view.php?eno=66703

Here's where you can reach us : svc@acsty2026.org  (or) svcconfe@yahoo.com

 

#Dsp #FpgaArchitecture #Embedded #FpgaBasedSystems #ImageProcessing #SpeechProcessing #VideoProcessing  #InformationProcessing  #InternetOfThings #MachineLearning #SignalProcessing  #RealTimeSystems #Robotics #SingleBoardComputerSystems #Callforpapers #2025Conference #Canada #DigitalSignalProcessing #AnalogSignal #FrequencyResolution #CharacteristicRoot #filterdesignfastFouriertransform #ElectricalSignaling #Plantelectricalsignals #Plantelectrophysiologicalphenotype  #TelecommunicationTransmissionSignals #Ancientsystemsoftelecommunication 


Monday, 29 December 2025

 *** Call For Papers ***

International Journal of Embedded Systems and Applications (IJESA)

ISSN : 1839-5171

H-index -10

Web Page URL : https://wireilla.com/ijesa/index.html

Submission Deadline: January 06, 2026

Submission URL :http://allcfps.com/wireilla/submission/index.php

Contact Us : ijesajournal@yahoo.com or ijesa@wireilla.com

#EmbeddedSystems #IoT #Automation #SystemDesign #Innovation #TechTrends #Microcontrollers #SoftwareEngineering #HardwareDesign #DigitalTransformation #SmartDevices #EdgeComputing #Industry4_0 #Electronics #Firmware #ControlSystems #Engineering #TechInnovation #ConnectedDevices #EmbeddedSoftware #RealTimeSystems #TechIndustry #SystemIntegration #TechSolutions #SmartTechnology #EmbeddedDevelopment #CyberSecurity #TechCommunity #Technology #futuretechnology


Friday, 26 December 2025

International Journal of Embedded Systems and Applications (IJESA)

#embeddedsystems #iot #microcontrollers #automation #smartdevices #techinnovation #embeddedengineering #digitaldesign #systemonchip #realtimesystems #firmwaredevelopment #hardwareintegration #techtrends #electronics #softwareengineering #robotics #controlsystems #dataacquisition #signalprocessing #techcommunity
International Journal of Embedded Systems and Applications (IJESA)
ISSN : 1839-5171
https://wireilla.com/ijesa/index.html
International Journal of Embedded Systems and Applications
https://www.scilit.com/sources/41447
https://www.scilit.com/publications/b6919d0f563ccec4cbacec443c8b57eb


 

Wednesday, 24 December 2025

PRACTICAL IMPLEMENTATION: PHASE LOCK LOOP AND A FEEDBACK LOOP BASED FULL COLOUR LASER TV

 Paper Title: 

PRACTICAL IMPLEMENTATION: PHASE LOCK LOOP AND A FEEDBACK LOOP BASED FULL COLOUR LASER TV

Authors: 

Oumair Naseer, 2Atif Ali Khan, 3 Mian Naeem-ul-Haq, 4Fawad Saleem, 5Ayesha Naseer

1 School of Engineering, University of Warwick, Coventry, UK,

Abstract:

In Multimedia society, the needs for large area display are increasing day by day. Many kinds of projection displays are now developed such as LCD, LCOS, DMD and Laser TV. Current Laser scanning projections methodologies is not efficient from cost, weight and power perspective. In this paper we have used low commercial microcontrollers with a scanning mirror (Progressive Scanning) technology. Three laser lights blue, green and red with wavelengths 457 nm, 532 nm and 648 nm are used. Power levels of lasers are adjusted for white color balance. Phase Lock Loop (PLL) with a feedback loop is used to synchronize horizontal (high speed brush-less DC motor) and vertical mirrors (stepper motor) pulses. The resulting Laser TV assembly is more efficient in terms of cost, power and weight.

KEYWORDS

Phase Lock Loop; Voltage Controlled Oscillation; Laser TV, Progressive Scanning.

Volume URL: https://wireilla.com/ijesa/vol3.html

https://airccse.org/journal/ijesa/papers/3213ijesa03.pdf

#Audio #AC97 #controller #Embedded #system #FPGA #MicroBlaze #Power #consumption #System #on #Chip #SoC #OpenCores #OpenRISC #researchpapers #cfp #researchers #phdstudent #education #learning #online #researchscholar #journalpaper #submission #journalsubmission #engineeringexcellence #techcommunity #devops #agilemethodology


Tuesday, 23 December 2025

12th International Conference on Image and Signal Processing (ISPR 2026)

 #imageprocessing #pcb #python #artificialintelligence #softwaredefinedradio #machinelearning #atmega #elektronikdevre #bme #programming #electronicprojects #designdaily #electronicsoundcommunicationengineering #engineeringstudents #tftdisplay #robotik #abletonlive #seo #viral #trending #shorts #digitalmarketing #epublishing

#ethernet #smarthome #bareconductive #steppermotor #weatherstation #sha #deeplearning #electricalwork #hackadayprize #arduinoprogramming #printedcircuitboards #solderingiron #asrockmotherboard
Welcome to ISPR 2026! Final Call!
12th International Conference on Image and Signal Processing (ISPR 2026)
January 17 ~ 18, 2026, Zurich, Switzerland
https://csita2026.org/ispr/index

 

Submission Deadline: December 27, 2025(Final Call)

 

Submission System: https://csita2026.org/submission/index.php

 

Contact Us
Here's where you can reach us: ispr@csita2026.org (or) confispr@yahoo.com


Monday, 22 December 2025

Call For Papers - International Journal of Embedded Systems and Applications (IJESA)

 *** Call For Papers ***

International Journal of Embedded Systems and Applications (IJESA)

ISSN : 1839-5171

H-index -10

Web Page URL : https://wireilla.com/ijesa/index.html

Submission Deadline: December 28, 2025

Submission URL :http://allcfps.com/wireilla/submission/index.php

Contact Us : ijesajournal@yahoo.com or ijesa@wireilla.com

#EmbeddedSystems #IoT #Automation #SystemDesign #Innovation #TechTrends #Microcontrollers #SoftwareEngineering #HardwareDesign #DigitalTransformation #SmartDevices #EdgeComputing #Industry4_0 #Electronics #Firmware #ControlSystems #Engineering #TechInnovation #ConnectedDevices #EmbeddedSoftware #RealTimeSystems #TechIndustry #SystemIntegration #TechSolutions #SmartTechnology #EmbeddedDevelopment #CyberSecurity #TechCommunity #Technology #futuretechnology


Wednesday, 17 December 2025

A New N-Fold Flip-Flop with Output Enable

 Paper Title:

A New N-Fold Flip-Flop with Output Enable
Authors:
Mounir Zid1, Carlo Pistritto2, Rached Tourki1 and Alberto Scandurra2
1University of Monastir, Tunisia and 2On Chip Communication Systems, Italy
Abstract:
With the evolution of the semiconductor industry and the continuous growing demands for high performance VLSI circuit, the aggressive scaling in feature size and high integration density along with the high operating frequencies make power consumption and digital noise in modern analog and digital devices one of the top concerns of Very Large Scale Integration (VLSI) circuit design. In this paper we delve into the design of n-fold flip-flops with output enable. A new n-fold flip-flop exploiting the clock gating technique for both outputs enabling and power saving is presented. To evaluate its performance, an octal flip-flop was built according to the new proposed structure and compared to the main octal flip-flops used today. The different flip-flops were implemented in STMicroelectronics 65 nm process technology and simulated for the worst case condition where the switching activity is maximal. Post layout simulation showed that the new circuit provides the same functional performances as conventional solutions with significantly less power consumption, area and digital noise.
KEYWORDS
Flip-flops; Output enabling; Low power design; Clock gating

Tuesday, 16 December 2025

10th International Conference on Signal, Image Processing (SIPO 2026)

****Registration is currently Open ****

 

#Callforpapers #2025Conference #Canada #DigitalSignalProcessing #AnalogSignal #FrequencyResolution #CharacteristicRoot #filterdesignfastFouriertransform #ElectricalSignaling #Plantelectricalsignals #Plantelectrophysiologicalphenotype  #TelecommunicationTransmissionSignals #Ancientsystemsoftelecommunication #thetransmissionofsignals #Radionetwork #Wirelessnetworks #5Gmobility #IoT #LiDAR #Wavetransformation #Waveenergy #LevelsofDataMeasurement #WorldWideWeb #Magnitude #SensorData #multipleSensorsystems

 

Welcome To SIPO 2025

 

Submit your Research Article..!!!

 

10th International Conference on Signal, Image Processing (SIPO 2026)

 

January 24 ~ 25, 2026, Copenhagen, Denmark

 

Webpage URL; https://aisca2026.org/sipo/index

 

Submission URL; https://aisca2026.org/submission/index.php

 

Contact Us : sipo@aisca2026.org