FPGA Real Time Acceleration for Discrete Wavelet Transform of the 5/3 Filter for JPEG2000 Standard

FPGA Real Time Acceleration for Discrete Wavelet Transform of the 5/3 Filter for JPEG2000 Standard

Taoufik Saidani, Mohamed Atri, Yahia Said and Rached Tourki FSM University, Tunisia

ABSTRACT

In recent years video and image compression have became very required . The availability of powerful software design tools is a fundamental requirement to take advantage of the many advanced and specialized resources included in the latest devices. Video acceleration and processing technologies have become critical for the development of many consumer electronics products. In this paper, we investigate Real Time FPGA implementation of 2-D lifting-based Daubechies 5/3 transforms using a Matlab/Simulink/Xilinx System Generator tool that generates synthesizable VHSIC Hardware Description. This system offers significant advantages: portability, rapid time to market and real time, continuing parametric change in the DWT transform.The proposed model has been designed and simulated using Simulink and System Generator blocks, synthesized with Xilinx Synthesis tool (XST) and implemented on Spartan 3A DSP based XCSD 3400A-4fg476 target device.

KEYWORDS JPEG2000 ,wavelet , FPGA, Matlab Xilinx System generator, VHDL. Original Source URL: http://airccse.org/journal/ijesa/papers/2112ijesa01.pdf https://wireilla.com/ijesa/vol2.html

Socs Based Openrisc and Microblaze Soft Processors Comparison Study Cases: Audio Implementation and Network Implementation Based Socs

Socs Based Openrisc and Microblaze Soft Processors Comparison Study Cases: Audio Implementation and Network Implementation Based Socs

Faroudja Abid, Nouma Izeboudjen, Dalila Lazib, Mohamed Bakiri, Sabrina Titri and Fatiha Louiz Microelectronic and Nanotechnology Laboratory, Algeria

ABSTRACT

The IP reuse approach and FPGA-platform-based SoC (System on Chip) with an embedded soft processor is an alternative to design SoCs that allows fast creation and verification. In this paper we address a comparison study between two SoCs architectures based OpenRISC (OpenCores) and MicroBlaze (proprietary) soft processors. The comparison is done for two applications, namely the audio and network applications based SoCs. The SoCs have been prototyped using the Virtex5 XC5VLX50 FPGA. Regarding the SoCs for audio application, the results show that slices are more used in the Open RISC based SoC while BRAM memories are more used in the SoC based MicroBlaze. Concerning the SoCs for Network application used slices register are slightly different in the two SoCs, BRAM memories and slice LUTs are more used in the OpenRISC based SoC. We notice that power consumption is better for the SoCs based MicroBlaze for the both applications

KEYWORDS Audio, AC97 controller, Embedded system, FPGA, MicroBlaze, Power consumption, System on Chip (SoC), OpenCores, OpenRISC Original Source URL: http://airccse.org/journal/ijesa/papers/3413ijesa02.pdf https://wireilla.com/ijesa/vol3.html

Performing an Experimental Platform to Optimize Data Multiplexing

Performing an Experimental Platform to Optimize Data Multiplexing

Remy Astier, Thierry Capitaine, Jerome Dubois, Valery Bourny, Aurelien Lorthois and Jerome Fortin Laboratoire des Technologies Innovantes, France

ABSTRACT

This article is based on preliminary work on the OSI model management layers to optimized industrialwired data transfer on low data rate wireless technology. Our previous contribution deal with thedevelopment of a demonstrator providing CAN bus transfer frames (1Mbps) on a low rate wireless channelprovided by Zigbee technology. In order to be compatible with all the other industrial protocols, wedescribe in this paper our contribution to design an innovative Wireless Device (WD) and a software tool,which will aim to determine the best architecture (hardware/software) and wireless technology to be usedtaking in account of the wired protocol requirements. To validate the proper functioning of this WD, wewill develop an experimental platform to test different strategies provided by our software tool. We canconsequently prove which is the best configuration (hardware/software) compared to the others by theinclusion (inputs) of the required parameters of the wired protocol (load, binary rate, acknowledge timeout) and the analysis of the WD architecture characteristics proposed (outputs) as the delay introducedby system, buffer size needed, CPU speed, power consumption, meeting the input requirement. It will beimportant to know whether gain comes from a hardware strategy with hardware accelerator e.g or asoftware strategy with a more performing scheduler. At the end, our experimental platform will be a toolfor characterizing different WD

KEYWORDS Embedded system, Multiplexing, Decision Support Tool, Test bench, Networking management systems Original Source URL: http://airccse.org/journal/ijesa/papers/3413ijesa01.pdf https://wireilla.com/ijesa/vol3.html

Dominant Block Guided Optimal Cache Size Estimation to Maximize IPC of Embedded Software

Dominant Block Guided Optimal Cache Size Estimation to Maximize IPC of Embedded Software

Rajendra Patel and Arvind Rajawat Maulana Azad National Institute of Technology, India

ABSTRACT

Embedded system software is highly constrained from performance, memory footprint, energy consumptionand implementing cost view point. It is always desirable to obtain better Instructions per Cycle (IPC).Instruction cache has major contribution in improving IPC. Cache memories are realized on the same chipwhere the processor is running. This considerably increases the system cost as well. Hence, it is required tomaintain a trade-off between cache sizes and performance improvement offered. Determining the numberof cache lines and size of cache line are important parameters for cache designing. The design space forcache is quite large. It is time taking to execute the given application with different cache sizes on aninstruction set simulator (ISS) to figure out the optimal cache size. In this paper, a technique is proposed toidentify a number of cache lines and cache line size for the L1 instruction cache that will offer best ornearly best IPC. Cache size is derived, at a higher abstraction level, from basic block analysis in the LowLevel Virtual Machine (LLVM) environment. The cache size estimated from the LLVM environment is crossvalidated by simulating the set of benchmark applications with different cache sizes in SimpleScalar’s outof-ordersimulator. The proposed method seems to be superior in terms of estimation accuracy and/orestimation time as compared to the existing methods for estimation of optimal cache size parameters (cacheline size, number of cache lines).

KEYWORDS Optimal Cache Size, Embedded Software, Design Space Exploration, Performance Estimation, DominantBlock Original Source URL: http://airccse.org/journal/ijesa/papers/3313ijesa03.pdf https://wireilla.com/ijesa/vol3.html

Evaluating the Performance and Behaviour of RT-XEN

Evaluating the Performance and Behaviour of RT-XEN

Hasan Fayyad-Kazan1, Luc Perneel1 and Martin Timmerman1,2 1Vrije Universiteit Brussel, Belgium 2Dedicated-Systems Experts Diepenbeemd 5, Belgium

ABSTRACT

Virtualization, together with real-time support emerges to be used in an increasing amount of use cases, varying from embedded systems to enterprise computing. One of the most popular open-source virtualization software’s is Xen. Its current implementation does not qualify it to be a candidate for timecritical systems. Researchers and developers extended it and claim the efficient usage of their versions in such systems. RT-Xen is one of these versions. It is a virtualization platform based on Compositional Scheduling and uses a suite of fixed-priority schedulers. This paper evaluates the performance and scheduling behaviour of RT-Xen. The test results show that only two proposed schedulers are suitable to be used for soft real-time applications.

KEYWORDS Embedded systems Original Source URL: http://airccse.org/journal/ijesa/papers/3313ijesa02.pdf https://wireilla.com/ijesa/vol3.html

Temporal Workload Analysis and its Application to Power-Aware Scheduling

Temporal Workload Analysis and its Application to Power-Aware Scheduling

Ye-In Seol1, Jeong-Uk Kim1 and Young-Kuk Kim2, 1Sangmyung University, South Korea 2Chungnam National University, South Korea

ABSTRACT

Power-aware scheduling reduces CPU energy consumption in hard real-time systems through dynamic voltage scaling(DVS). The basic idea of power-aware scheduling is to find slacks available to tasks and reduce CPU‟s frequency or lower its voltage using the found slacks. In this paper, we introduce temporal workload of a system which specifies how much busy its CPU is to complete the tasks at current time. Analyzing temporal workload provides a sufficient condition of schedulability of preemptive early-deadline first scheduling and an effective method to identify and distribute slacks generated by early completed tasks. The simulation results show that proposed algorithm reduces the energy consumption by 10-70% over the existing algorithm and its algorithm complexity is O(n). So, practical on-line scheduler could be devised using the proposed algorithm

KEYWORDS Power-aware Scheduling, Real-time Scheduling, Embedded Systems Original Source URL: http://airccse.org/journal/ijesa/papers/3313ijesa01.pdf https://wireilla.com/ijesa/vol3.html

Practical Implementation: Phase Lock Loop and a Feedback Loop Based Full Colour Laser Tv

Practical Implementation: Phase Lock Loop and a Feedback Loop Based Full Colour Laser Tv

Oumair Naseer1, Atif Ali Khan1, Mian Naeem-ul-Haq2, Fawad Saleem2 and Ayesha Naseer3 1University of Warwick, UK 2FAST-nu, Pakistan 3NUST, Pakistan

ABSTRACT

In Multimedia society, the needs for large area display are increasing day by day. Many kinds of projection displays are now developed such as LCD, LCOS, DMD and Laser TV. Current Laser scanning projections methodologies is not efficient from cost, weight and power perspective. In this paper we have used low commercial microcontrollers with a scanning mirror (Progressive Scanning) technology. Three laser lights blue, green and red with wavelengths 457 nm, 532 nm and 648 nm are used. Power levels of lasers are adjusted for white color balance. Phase Lock Loop (PLL) with a feedback loop is used to synchronize horizontal (high speed brush-less DC motor) and vertical mirrors (stepper motor) pulses. The resulting Laser TV assembly is more efficient in terms of cost, power and weight

KEYWORDS Phase Lock Loop; Voltage Controlled Oscillation; Laser TV, Progressive Scanning. Original Source URL: http://airccse.org/journal/ijesa/papers/3213ijesa03.pdf https://wireilla.com/ijesa/vol3.html

A New N-Fold Flip-Flop with Output Enable

A New N-Fold Flip-Flop with Output Enable

Mounir Zid1, Carlo Pistritto2, Rached Tourki1 and Alberto Scandurra2 1University of Monastir, Tunisia 2On Chip Communication Systems, Italy

ABSTRACT

With the evolution of the semiconductor industry and the continuous growing demands for high performance VLSI circuit, the aggressive scaling in feature size and high integration density along with the high operating frequencies make power consumption and digital noise in modern analog and digital devices one of the top concerns of Very Large Scale Integration (VLSI) circuit design. In this paper we delve into the design of n-fold flip-flops with output enable. A new n-fold flip-flop exploiting the clock gating technique for both outputs enabling and power saving is presented. To evaluate its performance, an octal flip-flop was built according to the new proposed structure and compared to the main octal flip-flops used today. The different flip-flops were implemented in STMicroelectronics 65 nm process technology and simulated for the worst case condition where the switching activity is maximal. Post layout simulation showed that the new circuit provides the same functional performances as conventional solutions with significantly less power consumption, area and digital noise

KEYWORDS Flip-flops; Output enabling; Low power design; Clock gating Original Source URL: http://airccse.org/journal/ijesa/papers/3213ijesa02.pdf https://wireilla.com/ijesa/vol3.html

Design of a Battery Charger Interface Precharge for Mobile Phone

Design of a Battery Charger Interface Precharge for Mobile Phone

Karim El khadiri and Hassan Qjidaa Sidi Mouhamed Ben Abdellah University, Morocco

ABSTRACT

This paper describes the analysis and design of a Battery Charger Interface Pre-charge (BCIP) for mobile phone. Battery charger interface pre-charge is very important function in the battery management integrated circuit, which allows the control of the charge of the battery with the maximum battery autonomy without reducing its life. The Battery Charger Interface Pre-charge has been designed and implemented in a 0.35µm CMOS technology and the active area of this circuit is about 1.54mm2

KEYWORDS Battery charger interface, Pre-charge, Band-gap, Comparator, Shunt-regulator Original Source URL: http://airccse.org/journal/ijesa/papers/3213ijesa01.pdf https://wireilla.com/ijesa/vol3.html

Experimental Implementation of Embarrasingly Parallel Process in Analysis of Blood Glucose Concentration Using Atmega32 Microcontrollers

Experimental Implementation of Embarrasingly Parallel Process in Analysis of Blood Glucose Concentration Using Atmega32 Microcontrollers

S. Kumaravel1 and P. Neelamegam2 1AVVM Sri Pushpam College (Autonomous), India 2Technology and Research Academy (SASTRA) Deemed University, India

ABSTRACT

This paper explains the development of a embedded based parallel system to measure glucose concentration of the blood samples. The developed instrument works on the principle of absorbance transmittance photometry using ATmega32 microcontrollers. In order to handle more blood samples and reduce the response time of glucose analyzing process in large number of blood samples, the embarrassing parallel measurement operation is implemented. The proposed system architecture and the co-design of hardware and software are discussed in detail. The system is evaluated using the parameters of Speedup Factor, Efficiency and Throughput are studied. The result shows that system attained the linear speedup in measurement of blood samples.

KEYWORDS Parallel Process, Embedded System, Glucose Concentration, Microcontroller, Clinical Blood Analyzer. Original Source URL: http://airccse.org/journal/ijesa/papers/3113ijesa04.pdf https://wireilla.com/ijesa/vol3.html

Hardware Acceleration of the Gipps Model for Real-Time Traffic Simulation

Hardware Acceleration of the Gipps Model for Real-Time Traffic Simulation

Salim Farah and Magdy Bayoumi, University of Louisiana at Lafayette, USA

ABSTRACT

Traffic simulation software is becoming increasingly popular as more cities worldwide use it to better manage their crowded traffic networks. An important requirement for such software is the ability to produce accurate results in real time, requiring great computation resources. This work proposes an ASICbased hardware accelerated approach for the AIMSUN traffic simulator, taking advantage of repetitive tasks in the algorithm. Different system configurations using this accelerator are also discussed. Compared with the traditional software simulator, it has been found to improve the performance by as much as 9x when using a single processing element approach, or more depending on the chosen hardware configuration.

KEYWORDS Traffic Simulation, Gipps Model, AIMSUN, ASIC Original Source URL: http://airccse.org/journal/ijesa/papers/3113ijesa03.pdf https://wireilla.com/ijesa/vol3.html

Hardware/Software Co-Design of a 2d Graphics System on FPGA

Hardware/Software Co-Design of a 2d Graphics System on FPGA

Kahraman Serdar Ay1 and Atakan Dodan2 1Tubitak Bilgem, Kocaeli, Turkey 2Anadolu University, Turkey

ABSTRACT

Embedded systems in several applications require a graphics system to display some application-specific information. Yet, commercial graphic cards for the embedded systems either incur high costs, or they are inconvenient to use. Furthermore, they tend to quickly become obsolete due to the advances in display technology. On the other hand, FPGAs provide reconfigurable hardware resources that can be used to implement graphics system in which they can be reconfigured to meet the ever-evolving requirements of graphics systems. Motivated from this fact, this study considers the design and implementation of a 2D graphics system on FPGA. The graphics system proposed is composed of a CPU IP core, peripheral IP cores (Bresenham, BitBLT, DDR Memory Controller, and VGA) and PLB bus to which CPU and all peripheral IP cores are attached. Furthermore, some graphics drivers and APIs are developed to complete the whole graphics creation process.

KEYWORDS Accelerator architectures, computer graphics, digital circuits, embedded software Original Source URL: http://airccse.org/journal/ijesa/papers/3113ijesa02.pdf https://wireilla.com/ijesa/vol3.html