Design and Implementation of a Wireless Sensor and Actuator Network for Energy Measurement and Control at Home

Design and Implementation of a Wireless Sensor and Actuator Network for Energy Measurement and Control at Home

Edwin Chobot, Daniel Newby, Renee Chandler, Nusaybah Abu-Mulaweh, Chao Chen and Carlos Pomalaza-Raez Indiana University - Purdue University Fort Wayne, USA

ABSTRACT

This paper describes the design, implementation, and testing of a wireless sensor and actuator network for monitoring the energy use of electric appliances in a home environment. The network includes energy measurement nodes and a central server, where the nodes read the energy use of connected appliance, and wirelessly report their readings to the central server for processing. The server displays the readings from these nodes via a user visual interface in real time. Through this system, users can easily understand their electricity usage patterns and adapt their behaviour to reduce their energy consumption and costs. Moreover, users are able to remotely power on/off individual devices to actively control the power use of certain appliances. The system allows for inexpensive monitoring of home energy use and illustrates a practical way to control the energy consumption through user interaction.

KEYWORDS Wireless sensor and actuator network, energy measurement, remote control, IEEE 802.15.4 Original Source URL: http://airccse.org/journal/ijesa/papers/3113ijesa01.pdf https://wireilla.com/ijesa/vol3.html

Automatic Analysis of Smoothing Techniques by Simulation Model Based Real-Time System for Processing 3D Human Faces

Automatic Analysis of Smoothing Techniques by Simulation Model Based Real-Time System for Processing 3D Human Faces

Suranjan Ganguly, Debotosh Bhattacharjee and Mita Nasipuri Jadavpur University, India

ABSTRACT

The pivotal research work that has been carried out and described in this literature acknowledges the importance of various smoothing techniques for processing 3D human faces from 2.5D range face images. The smoothing techniques have been developed and implemented using MATLAB-Simulink for real time processing in embedded system. In addition, the significance of smoothed 2.5D range image over original face range image has been discovered as well as its time complexity has also been reported with array of experiments. The variations in time complexities are also accomplished using different optimization levels and execution modes. A set of filtering techniques such as, Max filter, Min filter, Median filter, Mean filter, Mid-point filter and Gaussian filter, have been designed and illustrated using Simulink model. The model takes depth face image (i.e. the range face image) as input in real time and presents the improvement over original face images. In the design flow, the performance of every block has also been characterized by range face images from Frav3D, GavabDB, and Bosphorus databases. In the experimental section of this research article, an array of performance analysis for these smoothing techniques with variation of frameworks is explained.

KEYWORDS 3D face image, 2.5D face image, MATLAB-Simulink, Smoothing techniques, Range face image Original Source URL: http://airccse.org/journal/ijesa/papers/4414ijesa02.pdf http://airccse.org/journal/ijesa/current2014.html

A Case Study: Task Scheduling Methodologies for High Speed Computing Systems

A Case Study: Task Scheduling Methodologies for High Speed Computing Systems

Mahendra Vucha and Arvind Rajawat Maulana Azad National Institute of Technology, India

ABSTRACT

High Speed computing meets ever increasing real-time computational demands through the leveraging of flexibility and parallelism. The flexibility is achieved when computing platform designed with heterogeneous resources to support multifarious tasks of an application where as task scheduling brings parallel processing. The efficient task scheduling is critical to obtain optimized performance in heterogeneous computing Systems (HCS). In this paper, we brought a review of various application scheduling models which provide parallelism for homogeneous and heterogeneous computing systems. In this paper, we made a review of various scheduling methodologies targeted to high speed computing systems and also prepared summary chart. The comparative study of scheduling methodologies for high speed computing systems has been carried out based on the attributes of platform & application as well. The attributes are execution time, nature of task, task handling capability, type of host & computing platform. Finally a summary chart has been prepared and it demonstrates that the need of developing scheduling methodologies for Heterogeneous Reconfigurable Computing Systems (HRCS) which is an emerging high speed computing platform for real time applications

KEYWORDS High Speed Computing Systems, Heterogeneous Computing System, homogeneous Computing System, Reconfigurable Hardware, Scheduling, soft core processor, hard core processor Original Source URL: http://airccse.org/journal/ijesa/papers/4414ijesa01.pdf http://airccse.org/journal/ijesa/current2014.html

Fast Transient Response Low Drop-Out Voltage Regulator

Fast Transient Response Low Drop-Out Voltage Regulator

Hicham Akhamal, Mostafa Chakir, Hassan Qjidaa Sidi Mohamed Ben Abdellah University, Morocco

ABSTRACT

This paper presents the design of Low Drop-Out (LDO) voltage regulator has fast transient response and which exploits a few current else low quiescent current in the operational amplifier PMOS type. We use band-gap reference for eliminate the temperature dependence. The proposed LDO voltage regulator implemented in 0.18-µm CMOS technology, we use Folded cascode CMOS amplifiers high performance in the stability , provide fast transient response which explains a fast settling, the LDO itself should provide in the output regulator voltages at ∆t equal 2ps with transient variation of the voltage less than 170mV. High accuracy in the DC response terms, the simulation results show that the accuracy of the output regulator voltages is 1.54±0.009V, and power consumption of 1.51 mW

KEYWORDS Low-dropout (LDO ) voltage regulator, Band-gap reference, Fast transient response, Current efficiency, Figure of merit & Layout. Original Source URL: http://airccse.org/journal/ijesa/papers/4314ijesa01.pdf http://airccse.org/journal/ijesa/current2014.html

Generic SOPC Platform for Video Interactive System with Mpmc Controller

Generic SOPC Platform for Video Interactive System with Mpmc Controller

Lamjed Touil1,2, Lilia Kechiche1,2 and Bouraoui Ouni1,3 1University of Monastir, Tunisia 2National Engineering School of Monastir (ENIM), Tunisia3National Engineering School of Sousse (ENISo), Tunisia

ABSTRACT

Today, a significant number of embedded systems focus on multimedia applications with almost insatiable demand for low-cost, high performance, and low power hardware cosumption. In this paper, we present a re-configurable and generic hardware platform for image and video processing. The proposed platform uses the benefits offered by the Field Programmable Gate Array (FPGA) to attain this goal. In this context, a prototype system is developed based on the Xilinx Virtex-5 FPGA with the integration of embedded processors, embedded memory, DDR, interface technologies, Digital Clock Managers (DCM) and MPMC. The MPMC is an essential component for design performance tuning and real time video processing. We demonstrate the importance role of this interface in multi video applications. In fact, to successful the deployment of DRAM it is mandatory to use a flexible and scalable interface. Our system introduces diverse modules, such as cut video detection, video zoom-in and out. This provides the utility of using this architecture as a universal video processing platform according to different application requirements. This platform facilitates the development of video and image processing applications.

KEYWORDS MPMC, DDR, Cut Detection, Zoom-in, Zoom-out RGB, Image Processing Original Source URL: http://airccse.org/journal/ijesa/papers/4114ijesa02.pdf http://airccse.org/journal/ijesa/current2014.html

Simple Hand-Held Calculating Unit to Aid the Visually Impaired with Voice Output

Simple Hand-Held Calculating Unit to Aid the Visually Impaired with Voice Output

Shreedeep Gangopadhyay, Molay Kumar Mondal and Arpita Pramanick Techno India, Salt Lake, India Professor, IIITM-K, Trivandrum, India

ABSTRACT

A thorough understanding in mathematics enhances educational and occupational opportunities for all,whether sighted or visually impaired.. However, solving complicated mathematical problems is difficult forvisually challenged students in schools and universities as the calculators available in the markets with smooth input keys and LCD outputs are useless for them. Using the assistive technology which is basicallya service or product to help people with disabilities function more independently has removed barriers toeducate and employ people. An optimal solution for them is Braille calculator with audio output. In thispaper, we have proposed a cost effective, hand-held, battery-driven, low power assistive device aiming thevisually impaired people from low income settings. The input is given through a 4 by 4 Membrane keypadwhich has been Braille-embossed using indigenous methods. The output is announced in natural English bythe audio unit via speakers and/or headphones up to two places of decimal point. The system is implemented on custom made open source Arduino platform, making it efficient and cost-effective.

KEYWORDS Braille Keypad, calculator, Arduino, assistive technology, visually challenged. Original Source URL: http://airccse.org/journal/ijesa/papers/5315ijesa01.pdf http://airccse.org/journal/ijesa/current2015.html

Design Challenges in Wireless Fire Security Sensor Nodes

Design Challenges in Wireless Fire Security Sensor Nodes

S.R.Vijayalakshmi and S.Muruganand Bharathiar University, India

ABSTRACT

A design of simple hardware circuit with differentkind of fire sensors enables every user to use thiswireless fire security system. The challenges in designing the nodes with various types of fire sensors arediscussed and the methods to overcome design proble ms are also analyzed. The circuit is interfaced withthe different types of sensor to sense different fire sources such as gas leakage, smoke, and heat. The cost,circuit components, design requirements, power requirements of sensor node are minimized. The methods to improve the quality of system to detect fire areanalyzed. The system is fully controlled by the PICmicrocontroller. All the sensors and detectors areinterconnected to PIC microcontroller by using varioustypes of interface circuits. The PIC microcontroller will continuously monitor all the sensors and ifit sensesany security problem then the microcontroller willsend the information to the PC central monitoringstation wirelessly for a short distance of 300m indoor/1500m outdoor using zigbee technology. The gassensor, light sensor, smoke detector sensor, IR sensor, temperature & humidity sensor, fire sensor areinterfaced with microcontroller to detect abnormalfire conditions in the environment in all possibleways

KEYWORDS Security Systems - Smoke Sensor – wireless sensor nodes – wireless fire security sensor nodes Original Source URL: http://airccse.org/journal/ijesa/papers/5215ijesa03.pdf http://airccse.org/journal/ijesa/current2015.html

Comparison and Evaluation of Digital Signature Schemes Employed in NDN Network

Comparison and Evaluation of Digital Signature Schemes Employed in NDN Network

Al Imem Ali H. Sousse University of Sousse, Tunisia

ABSTRACT

It is well known that Named Data networking ensure data integrity so that every important data has to besigned by its owner in order to send it safely inside the network. Similarly, in NDN we have to assure thatnone could open the data except authorized users. Since only the endpoints have the right to sign the data or check its validity during the verification process , we have considered that the data could be requested from various types of devices used by different people, these devices could be anything like a smartphone, PC, sensor node etc.b, with a different CPU descriptions, parameters, and memory sizes, however their ability to check the high traffic of a data during the key generation and/or verification period is definitely a hard task and it could exhaust the systems with low computational resources. RSA and ECDSA as digital signature algorithms have proven their efficiency against cyber-attacks, they are characterized by their speed to encrypt and decrypt data, in addition to their competence at checking the data integrity. The main purpose of our research was to find the optimal algorithm that avoids the system’s overhead and offers the best time during the signature scheme

KEYWORDS RSA, ECDSA, NDN, MSS, Digital signature algorithms, Security,Encryption, Decryption, Merkle scheme, Eliptic Curve Original Source URL: http://airccse.org/journal/ijesa/papers/5215ijesa02.pdf http://airccse.org/journal/ijesa/current2015.html

An Efficient Hybrid Scheduler Using Dynamic Slack for Real-Time Critical Task Scheduling in Multicore Automotive ECUs

An Efficient Hybrid Scheduler Using Dynamic Slack for Real-Time Critical Task Scheduling in Multicore Automotive ECUs

Geetishree Mishra1, Manasa RamPrasad2, Ashwin Itagi3 and K S Gurumurthy4, 1BMS College of Engineering, India, 2ABB India Limited, India3CISCO Systems, India 4Reva Intitute of Technology, India

ABSTRACT

Task intensive electronic control units (ECUs) in automotive domain, equipped with multicore processors ,real time operating systems (RTOSs) and various application software, should perform efficiently and time deterministically. The parallel computational capability offered by this multicore hardware can only be exploited and utilized if the ECU application software is parallelized. Having provided with such parallelized software, the real time operating system scheduler component should schedule the time critical tasks so that, all the computational cores are utilized to a greater extent and the safety critical deadlinesare met. As original equipment manufacturers (OEMs) are always motivated towards adding moresophisticated features to the existing ECUs, a large number of task sets can be effectively scheduled for execution within the bounded time limits. In this paper, a hybrid scheduling algorithm has been proposed,that meticulously calculates the running slack of every task and estimates the probability of meeting deadline either being in the same partitioned queue or by migrating to another. This algorithm was run and tested using a scheduling simulator with different real time task models of periodic tasks . This algorithmwas also compared with the existing static priority scheduler, which is suggested by Automotive OpenSystems Architecture (AUTOSAR). The performance parameters considered here are, the % of coreutilization, average response time and task deadline missing rate. It has been verified that, this proposedalgorithm has considerable improvements over the existing partitioned static priority scheduler based on each performance parameter mentioned above.

KEYWORDS ECU, Multicore, RTOS, Scheduling, OEM, AUTOSAR. Original Source URL: http://airccse.org/journal/ijesa/papers/5215ijesa01.pdf http://airccse.org/journal/ijesa/current2015.html

A Novel Methodology for Task Distribution in Heterogeneous Reconfigurable Computing System

A Novel Methodology for Task Distribution in Heterogeneous Reconfigurable Computing System

Mahendra Vucha1 and Arvind Rajawat2 1MANIT University India 2Christ University, India

ABSTRACT

Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems(HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core processors acts as computing elements. So, an efficient task distribution methodology is essential forobtaining high performance in modern embedded systems. In this paper, we present a novel methodologyfor task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a listbased dynamic scheduling algorithm that uses attributes of tasks as well computing resources as costfunction to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDMtransmitters are represented as task graph and then the task are distributed, statically as well dynamically,to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparisonshows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and alsospeedup an application execution

KEYWORDS Heterogeneous Reconfigurable Computing Systems, FPGA, parallel processing, concurrency, Directed Acyclic Graph. Original Source URL: http://airccse.org/journal/ijesa/papers/5115ijesa02.pdf http://airccse.org/journal/ijesa/current2015.html

Time Critical Multitasking For Multicore Microcontroller Using Xmos® Kit

Time Critical Multitasking For Multicore Microcontroller Using Xmos® Kit

Prerna Saini1, Ankit Bansal2 and Abhishek Sharma1, 1LNM Institute of Information Technology,India 2GLA University, India

ABSTRACT

This paper presents the research work on multicore microcontrollers using parallel, and time critical programming for the embedded systems. Due to the high complexity and limitations, it is very hard to work on the application development phase on such architectures. The experimental results mentioned in the paper are based on xCORE multicore microcontroller form XMOS®. The paper also imitates multi-tasking and parallel programming for the same platform. The tasks assigned to multiple cores are executed simultaneously, which saves the time and energy. The relative study for multicore processor and multicore controller concludes that micro architecture based controller having multiple cores illustrates better performance in time critical multi-tasking environment. The research work mentioned here not only illustrates the functionality of multicore microcontroller, but also express the novel technique of programming, profiling and optimization on such platforms in real time environments .

KEYWORDS Multicore microcontroller, xCORE, xTIMEcomposer, Multitasking, Parallel programming, Time slicing, Embedded System, Time critical programming. Original Source URL: http://airccse.org/journal/ijesa/papers/5115ijesa01.pdf http://airccse.org/journal/ijesa/current2015.html

DESIGN AND PROTOTYPE OF A WIRELESS TAILGATE DETECTION SYSTEM USING SUN SPOT PLATFORM

DESIGN AND PROTOTYPE OF A WIRELESS TAILGATE DETECTION SYSTEM USING SUN SPOT PLATFORM Andres Alarcon-Ramirez, Madeline Martinez-Pabón and Charles Kim Department of Electrical Engineering, Howard University, Washington DC ABSTRACT

In this paper, we present the design and implementation of a wireless sensor based piggybacking and tailgating detection system to detect unauthorized attempt to gain access to a secured area. A set of Sun SPOT wireless sensor platform is adopted for acceleration sensor, transmitter, and receiver units for the system. A wireless sensor embedded in a security door collects the signal of door movement constantly and transmits the signal wirelessly to another wireless sensor (base unit), which collects the transmitted signals and stores them in the memory of the computer system for analysis. The acceleration signal is analyzed in both time and frequency domain to detect and classify single and tailgate entries. The paper focuses on the description of the wireless sensor network and the sensor-based tailgate detection algorithm.

KEYWORDS Tailgate, piggybacking, embedded system, wireless sensor network, acceleration sensor. Original Source Link: http://airccse.org/journal/ijesa/papers/0811ijesa01.pdf http://wireilla.com/ijesa/vol1.html

A REVIEW ON ZIGBEE, GSM AND WSN BASED HOME SECURITY BY USING EMBEDDED CONTROLLED SENSOR NETWORK

A REVIEW ON ZIGBEE, GSM AND WSN BASED HOME SECURITY BY USING EMBEDDED CONTROLLED SENSOR NETWORK Anjali Kulkarni and Amol Patange Department of Electronics and Telecommunication Engineering, S.R.T.M University, India ABSTRACT

Embedded controlled detector network is that the technology needs to implement environmental solutions effectively. The wireless sensor network is used to control respective devices and monitor environmental parameters effectively. Wireless sensor network technology is used to monitor environmental parameters such temperature sound pressure in many applications. Many researchers are developed the wireless sensor network to implement real time surveillance for many applications. The existing wired systems are bulky, very high cost and difficult to maintain. The proposed system is user friendly, low cost and controlled by embedded controlled sensor network. In the proposed system ARM based microcontroller is used for monitoring and wireless sensors are used to control the various devices.

KEYWORDS

Zigbee, GSM, WSN, and Embedded controlled sensor network.

Original Source URL http://aircconline.com/ijesa/V6N4/6416ijesa01.pdf http://wireilla.com/ijesa/vol6.html

Developing Scheduler Test Cases To Verify Scheduler Implementations In Time-triggered Embedded Systems

Developing Scheduler Test Cases To Verify Scheduler Implementations In Time-triggered Embedded Systems

Mouaaz Nahas¹ and Ricardo Bautista-Quintero²

¹College of Engineering and Islamic Architecture, KSA, ²Department of Mechanical Engineering, InstitutoTecnólogico De Culiacán, Sinaloa

Abstract

Despite that there is a “one-to-many” mapping between scheduling algorithms and scheduler implementations, only a few studies have discussed the challenges and consequences of translating between these two system models. There has been an argument that a wide gap exists between scheduling theory and scheduling implementation in practical systems, where such a gap must be bridged to obtain an effective validation of embedded systems. In this paper, we introduce a technique called “Scheduler Test Case” (STC) aimed at bridging the gap between scheduling algorithms and scheduler implementations in single processor embedded systems implemented using Time-Triggered Co-operative (TTC) architectures. We will demonstrate how the STC technique can provide a simple and systematic way for documenting, verifying (testing) and comparing various TTC scheduler implementations on particular hardware. However, STC is a generic technique that provides a black-box tool for assessing and predicting the behavior of representative implementation sets of any real-time scheduling algorithm.

Keywords

Scheduler algorithm, scheduler implementation, cyclic executive, time-triggered co-operative scheduler, resource-constrained embedded system, scheduler test cases, predictability, jitter, task overrun.

Original Source URL: http://aircconline.com/ijesa/V6N1/6116ijesa01.pdf http://wireilla.com/ijesa/vol6.html

A Level Training Set with both a Computer-Based Control and a Compact Controller

A Level Training Set with both a Computer-Based Control and a Compact Controller

Hayati Mamur¹, Ismail Atacak², Fatih Korkmaz³ and M. R. Amin Bhuiyan¹

¹Manisa Celal Bayar University, Turkey, ²Gazi University, Turkey and ³Cankiri Karatekin University, Turkey

Abstract

In engineering education, the combination with theoretical education and practical education is an essential problem. The taught knowledge can be quickly forgotten without an experimental application. In addition, the theoretical knowledge’s cannot be easily associated applications by students when they start working in industry. To eliminate these problems, a number of education tools have been developed in engineering education. This article presents a modeling, simulation and practice study of a newly designed liquid level training set developed for the control engineering students to simulate, examine and analyze theoretically and experimentally the controllers widely used in the control of many industrial processes.The newly designed training set combines two control structures, which are a computer-based control and a digital signal processing-based control. The set displays the results related to experiments in real time as well as. These features have made it a suitable laboratory component on which the students can both simulate and test the performance of liquid level control systems by using theoretical different control structures.

Keywords

Computer-aided engineering, Computer-based control, DSP-based control, Engineering education, Process control

Original Source URL: http://aircconline.com/ijesa/V7N1/7117ijesa01.pdf http://wireilla.com/ijesa/current.html

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International Journal of Embedded Systems and Applications (IJESA)

ISSN : 1839 – 5171

http://wireilla.com/ijesa/index.html  

Scope & Topics

International Journal of Embedded Systems and Applications (IJESA) is a quarterly open access peer-reviewed journal that publishes articles which contribute new results in all areas of the Embedded Systems and applications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on understanding Embedded Systems and establishing new collaborations in these areas.

Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of Embedded Systems & applications.

Topics of interest include but are not limited to, the following

• Application-specific processors and devices
• Business Applications
• Component and binding models
• Embedded computing education
• Embedded hardware support
• Embedded software
• Embedded system architecture
• Hardware and software co-design
• Industrial practices and benchmark suites
• Integration with business logic
• Integration with SOA
• Middleware
• Networked Embedded Systems
• Policy-based management
• Programming abstractions
• Real-time systems
• Recent Trends
• Service-Oriented Architectures
• Testing techniques

Paper Submission

Authors are invited to submit papers for this journal through the Submission system. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates

• Submission Deadline    :  May 12, 2018
• Notification                  :  June 12, 2018
• Final Manuscript Due   : June 20, 2018
• Publication Date           : Determined by the Editor-in-Chief