Mehdi Alipour1 and Hojjat Taghdisi2 1Allameh Rafiei Highr Education Institute of Qazin, Iran 2Qazvin Islamic Azad University, Iran
ABSTRACT
According to the increasing complexity of network application and internet traffic, network processor as asubset of embedded processors have to process more computation intensive tasks. By scaling down thefeature size and emersion of chip multiprocessors (CMP) that are usually multi-thread processors, theperformance requirements are somehow guaranteed. As multithread processors are the heir of uni-threadprocessors and there isn’t any general design flow to design a multithread embedded processor, in thispaper we perform a comprehensive design space exploration for an optimum uni-thread embeddedprocessor based on the limited area and power budgets. Finally we run multiple threads on thisarchitecture to find out the maximum thread level parallelism (TLP) based on performance per power and area optimum uni-thread architecture.
KEYWORDS Embedded processor; cache; register file; multithread architecture; performance per power Original Source URL: http://airccse.org/journal/ijesa/papers/2112ijesa02.pdf https://wireilla.com/ijesa/vol2.html